1. Field of the Invention
The present invention generally relates to the design of electronic circuits such as integrated circuits. More particularly, the present invention relates to the functionality testing of electronic circuits during circuit design to ensure correct operation.
2. State of the Art
It is known to test the functionality of a circuit for correct operation. In practice, integrated circuits can be any of several silicon technologies, such as CMOS, Bipolar, GaAs, and so forth.
Integrated circuit manufacturers have developed methods such as gate array, cell and programmable logic based methods to reduce design time. Instead of custom designing a circuit by each individual transistor, which increases design time, most manufacturers have designed and characterized many basic, or primitive, functional blocks that can be used to build larger functional blocks. As this technique has evolved, larger functional blocks such as RAMs, ROMs, ALUs, and so forth have also been developed and characterized as primitive blocks.
Since most of these functional blocks can be of various characteristics (i.e., variable number of bits, number of words, speed, and so forth), many manufacturers have created compilers whereby gate array and cell-based designs can be composed from characterized functional blocks. These advancements coupled with Computer Aided Design (CAD) advancements have led customers to the design of their own integrated circuits for their specific application, known as Application Specific Integrated Circuits (ASICs), to further reduce design time.
Following the design of an application specific integrated circuit, it is desirable to test the functionality of the circuit for compliance with predetermined operational criteria. In order to test the functionality of a circuit formed, for example, on a semiconductor chip, the circuit is initially simulated in a test environment wherein test vectors are run for each cell. Simulation is performed to debug a circuit design and remove errors, such as errors in logic and timing. Following circuit simulation, test vectors are again used during manufacture to ensure proper implementation of, for example, a semiconductor wafer or assembled IC.
A test vector is a series of input signals to a given cell which will produce a known output or outputs from the cell. Accordingly, through the input of test vectors and by checking the outputs of the cell, the functionality of the cell can be determined.
Typically, an ASIC of the large scale integration or very large integration class will include a number of very similar and/or identical cells. For example, a given circuit may include a number of the same RAMs, two or more of the same multipliers, two or more of the same adders, and so forth. To test the functionality of the circuit, a test mode is normally initiated wherein each cell is sequentially isolated. Test vectors are then applied to each isolated cell one at a time. After testing the functionality of a given cell, test vectors are applied as stimuli for a subsequent cell, which may be similar or identical to a previously tested cell. Thus, when testing the functionality of a circuit having a number of similar or identical cells, the test vectors associated with these cells are run independently for each identical cell.
One characteristic of an integrated circuit is that the outputs of any given cell may go either to output pins of the circuit (e.g., chip output pins) or, to other internal cells of the circuit. The cells which are directly connected to output pins of a circuit may have their outputs tested relatively easily. However, isolation of those cells which are internally connected to other cells requires the use of additional circuitry to permit independent testing during manufacture. Accordingly, the requirement of independently run test vectors for each identical cell of a circuit layout not only increases the simulation time and number of test vectors required, but in addition, the hardware required to independently isolate each of the cells for independent testing increases the cost of the circuit.
For example, if a given cell requires 10,000 vectors to test its functionality, a minimum of 20,000 vectors would be required to test two identical cells contained in the circuit. The running of these 20,000 vectors directly impacts the design simulation time (i.e., a minimum of two times the time required for testing one cell). Further, some of the logic used for isolating a cell will have relatively slow speeds. For example, large multiplexers are typically required to permit independent isolation of each cell, and these large multiplexers can cause timing problems within the circuit during use of the chip.
Accordingly, there currently exists a need for a technique that will reduce the simulation time and number of test vectors required for testing the functionality of a circuit such that the time and cost of designing and testing the circuit can be reduced.